1. Field of the Invention
The present invention relates to signal processing and, particularly, to a technique of signal processing necessary to generate a plurality of synchronized clocks.
2. Description of Related Art
In the MPEG (Moving Picture Coding Experts Group) system that is applied to broadcasting and communication systems, storage media and so on, a clock called an STC (System Time Clock) is used because it is necessary to play back videos and sounds in synchronization with each other. For example, in the MPEG-2 system, the frequency of an STC is defined to be 27 MHz. Thus, receiving apparatus and playback apparatus in conformity with the MPEG-2 system conduct video signal processing and audio signal processing in synchronization with a 27-MHz STC. As a technique to achieve the synchronization, a receiving end generates a clock for video signal processing and a clock for audio signal processing based on a reference clock and supplies the clocks to a video signal processing circuit and an audio signal processing circuit, respectively (cf. Japanese Unexamined Patent Application Publication No. 2003-87229).
On the other hand, various kinds of standards are operated in combination in actual broadcasting. For example, in the ATSC (Advanced Television Systems Committee), which is a digital broadcasting system in the United States, MPEG-2 TS (Transport Stream), MPEG-2 Video, AC-3 (Audio Code number 3) are employed as a multiplexing system, a video compression system and an audio compression system, respectively. Further, a large number of video systems from the traditional NTSC (National Television Standards Committee) system to the HDTV (High Definition Television) system are defined as a video system, and two kinds of field rates, 59.94 Hz and 60 Hz, which are compatible with the NTSC system, are specified, and they are operated in combination (cf. Japanese Unexamined Patent Application Publication No. 2006-180005).
FIG. 9 shows several examples of the ATSC system. As an example of the 59.94 Hz system, in the case where a broadcast signal is “the resolution: 640×480, the scan mode: progressive, the frame rate: 60/1.001 (which is shown as 59.94 in the figure) Hz” shown in FIG. 9, about 59.94 frames of video in 640×480 pixels in each frame are displayed per one second. In actuality, however, because a video signal processing circuit performs processing including a portion that is not displayed on a screen, which is called a blanking period, the number of horizontal pixels is 858 and the total number of lines is 525 including the blanking period. Accordingly, a frequency (dot clock) that is necessary for the video signal processing circuit to perform the above processing for each pixel is 27 MHz as shown in the following Expression (1):858×525×60/1.001=27 MHz  Expression (1)
Further, an example of the 60 Hz system, in the case where a broadcast signal is “the resolution: 640×480, the scan mode: progressive, the frame rate: 60 Hz” shown in FIG. 9, the necessary dot clock is 27×1.001 MHz as shown in the following Expression (2):858×525×60=27×1.001 MHz  Expression (2)
In the receiving apparatus that receives broadcast signals with different dot clocks, it is necessary to generate dot clocks for the broadcast signals that are synchronized with an STC so as to deal with any of the broadcast signals.
A general method of generating a dot clock is to multiply and divide the frequency of a reference clock using a PLL (Phase-Locked Loop) circuit. In the system that aims at generating a clock synchronized with an STC, a reference clock is generally 27 MHz. Further, a technique of generating a desired clock by connecting two PLL circuits in series is disclosed in Japanese Unexamined Patent Application Publication No. 2000-350119.
Generation of various clocks in a receiving apparatus that receives broadcast signals of 59.94 Hz and 60 Hz described above is as follows.
FIG. 10 shows an example of a receiving apparatus. The receiving apparatus 1 includes a clock generator 10 that generates a reference clock, a system circuit 22, a video signal processing circuit 24, an audio signal processing circuit 26, an STC counter 30, a PLL circuit A that generates a clock to be used by the system circuit 22, a PLL circuit B that generates a clock (dot clock) to be used by the video signal processing circuit 24, and a PLL circuit C that generates a clock (audio clock) to be used by the audio signal processing circuit 26.
As described earlier, a dot clock of a video signal contained in a broadcast signal may have a plurality of different values. In the receiving apparatus 1 shown in FIG. 10, in order to deal with four kinds of dot clocks: 1: 74.25 MHz, 2: 74.25/1.001 MHz, 3: 27 MHz and 4: 27×1.001 MHz, the PLL circuit B that generates a dot clock needs to generate the four kinds of dot clocks.
FIG. 11 shows a frequency multiplication number and a frequency division number when the PLL circuit B generates the above-described four kinds of dot clocks based on the reference clock of 27 MHz. As shown therein, the frequency multiplication number and the frequency division number that are necessary for the PLL circuit B to generate the dot clock of 74.25 MHz based on the reference clock of 27 MHz are 44 and 16, respectively. The frequency multiplication number and the frequency division number are expressed hereinafter as “frequency multiplication number/frequency division number”. The “frequency multiplication number/frequency division number” necessary for the PLL circuit B to generate the dot clocks of 74.25/1.001 MHz, 27 MHz and 27×1.001 MHz are “250/91”, 2/2” and “1001/1000”, respectively.
In the field of image processing, there is a technique called DDA (Digital Differential Analysis) that is used for drawing a line shape at high speed. The technique is applicable to generation of pulses at equal intervals (cf. Japanese Unexamined Patent Application Publication No. 9-130636)